mirror of
https://github.com/DrKLO/Telegram.git
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232 lines
7.3 KiB
C++
232 lines
7.3 KiB
C++
/* Copyright (c) 2018, Google Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
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#include "cpu-arm-linux.h"
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#include <string.h>
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#include <gtest/gtest.h>
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TEST(ARMLinuxTest, CPUInfo) {
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struct CPUInfoTest {
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const char *cpuinfo;
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unsigned long hwcap;
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unsigned long hwcap2;
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bool broken_neon;
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} kTests[] = {
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// https://crbug.com/341598#c33
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{
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"Processor: ARMv7 Processory rev 0 (v71)\n"
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"processor: 0\n"
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"BogoMIPS: 13.50\n"
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"\n"
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"Processor: 1\n"
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"BogoMIPS: 13.50\n"
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"\n"
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"Features: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 "
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"idiva idivt\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 7\n"
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"CPU variant: 0x1\n"
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"CPU part: 0x04d\n"
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"CPU revision: 0\n"
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"\n"
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"Hardware: SAMSUNG M2\n"
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"Revision: 0010\n"
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"Serial: 00001e030000354e\n",
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HWCAP_NEON,
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0,
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true,
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},
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// https://crbug.com/341598#c39
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{
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"Processor : ARMv7 Processor rev 0 (v7l)\n"
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"processor : 0\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"Features : swp half thumb fastmult vfp edsp neon vfpv3 tls "
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"vfpv4\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 7\n"
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"CPU variant : 0x1\n"
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"CPU part : 0x04d\n"
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"CPU revision : 0\n"
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"\n"
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"Hardware : SAMSUNG M2_ATT\n"
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"Revision : 0010\n"
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"Serial : 0000df0c00004d4c\n",
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HWCAP_NEON,
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0,
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true,
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},
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// Nexus 4 from https://crbug.com/341598#c43
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{
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"Processor : ARMv7 Processor rev 2 (v7l)\n"
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"processor : 0\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"processor : 1\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"processor : 2\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"processor : 3\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"Features : swp half thumb fastmult vfp edsp neon vfpv3 tls "
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"vfpv4 \n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 7\n"
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"CPU variant : 0x0\n"
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"CPU part : 0x06f\n"
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"CPU revision : 2\n"
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"\n"
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"Hardware : QCT APQ8064 MAKO\n"
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"Revision : 000b\n"
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"Serial : 0000000000000000\n",
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HWCAP_NEON,
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0,
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false,
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},
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// Razr M from https://crbug.com/341598#c43
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{
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"Processor : ARMv7 Processor rev 4 (v7l)\n"
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"processor : 0\n"
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"BogoMIPS : 13.53\n"
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"\n"
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"Features : swp half thumb fastmult vfp edsp neon vfpv3 tls "
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"vfpv4\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 7\n"
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"CPU variant : 0x1\n"
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"CPU part : 0x04d\n"
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"CPU revision : 4\n"
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"\n"
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"Hardware : msm8960dt\n"
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"Revision : 82a0\n"
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"Serial : 0001000201fe37a5\n",
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HWCAP_NEON,
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0,
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false,
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},
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// Pixel 2 (truncated slightly)
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{
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"Processor : AArch64 Processor rev 1 (aarch64)\n"
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"processor : 0\n"
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"BogoMIPS : 38.00\n"
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"Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 8\n"
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"CPU variant : 0xa\n"
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"CPU part : 0x801\n"
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"CPU revision : 4\n"
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"\n"
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"processor : 1\n"
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"BogoMIPS : 38.00\n"
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"Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 8\n"
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"CPU variant : 0xa\n"
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"CPU part : 0x801\n"
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"CPU revision : 4\n"
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"\n"
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"processor : 2\n"
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"BogoMIPS : 38.00\n"
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"Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 8\n"
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"CPU variant : 0xa\n"
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"CPU part : 0x801\n"
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"CPU revision : 4\n"
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"\n"
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"processor : 3\n"
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"BogoMIPS : 38.00\n"
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"Features : fp asimd evtstrm aes pmull sha1 sha2 crc32\n"
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"CPU implementer : 0x51\n"
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"CPU architecture: 8\n"
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"CPU variant : 0xa\n"
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"CPU part : 0x801\n"
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"CPU revision : 4\n"
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// (Extra processors omitted.)
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"\n"
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"Hardware : Qualcomm Technologies, Inc MSM8998\n",
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HWCAP_NEON, // CPU architecture 8 implies NEON.
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HWCAP2_AES | HWCAP2_PMULL | HWCAP2_SHA1 | HWCAP2_SHA2,
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false,
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},
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// Nexus 4 from
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// Garbage should be tolerated.
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{
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"Blah blah blah this is definitely an ARM CPU",
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0,
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0,
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false,
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},
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// A hypothetical ARMv8 CPU without crc32 (and thus no trailing space
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// after the last crypto entry).
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{
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"Features : aes pmull sha1 sha2\n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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HWCAP2_AES | HWCAP2_PMULL | HWCAP2_SHA1 | HWCAP2_SHA2,
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false,
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},
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// Various combinations of ARMv8 flags.
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{
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"Features : aes sha1 sha2\n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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HWCAP2_AES | HWCAP2_SHA1 | HWCAP2_SHA2,
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false,
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},
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{
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"Features : pmull sha2\n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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HWCAP2_PMULL | HWCAP2_SHA2,
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false,
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},
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{
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"Features : aes aes aes not_aes aes aes \n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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HWCAP2_AES,
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false,
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},
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{
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"Features : \n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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0,
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false,
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},
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{
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"Features : nothing\n"
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"CPU architecture: 8\n",
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HWCAP_NEON,
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0,
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false,
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},
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};
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for (const auto &t : kTests) {
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SCOPED_TRACE(t.cpuinfo);
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STRING_PIECE sp = {t.cpuinfo, strlen(t.cpuinfo)};
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EXPECT_EQ(t.hwcap, crypto_get_arm_hwcap_from_cpuinfo(&sp));
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EXPECT_EQ(t.hwcap2, crypto_get_arm_hwcap2_from_cpuinfo(&sp));
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EXPECT_EQ(t.broken_neon ? 1 : 0, crypto_cpuinfo_has_broken_neon(&sp));
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}
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}
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